When scaling for next generation semiconductor devices in connection with increased miniaturization, including, for example, very-large-scale integration (VLSI), gate resistance can be a critical issue affecting device performance. As transistors scale down, the gate resistance increases considerably and becomes the limiting factor of gate delay.
According to conventional processing, increasing a height of a gate metal leads to large levels of gate to contact (e.g., source/drain contact) parasitic capacitance. Decreasing a height of the gate metal reduces parasitic capacitance, but increases gate resistance, causing unwanted gate delay.
Accordingly, there is a need for a semiconductor device and a method of manufacturing same which reduces gate to contact capacitance without causing unwanted increases in gate resistance.